Various mechanisms are known for electrically and mechanically connecting (or coupling) an integrated circuit to a supporting substrate (or major substrate). A common arrangement used for this purpose has solder bumps disposed on the IC chip and the supporting substrate in a corresponding relationship such that the surfaces of the chip and substrate are parallel. An example of this arrangement is the Controlled Collapsed Chip Connection process, which is abbreviated as the "C-4" or "C.sup.4 " process. The chip may be mounted to the supporting substrate such that the active surface of the chip, i.e., the structure which has the integrated components, faces away from the substrate or faces towards the substrate ("flip-chip"). In the first case, the signal and power lines from the active surface of the chip are brought to the periphery of the chip, and then connected to the supporting substrate by wirebonds or Tape Automated Bonding ("TAB") circuits. In the latter case of a "flip-chip" orientation, conductive pads on the active surface of the IC chip contact solder bumps on the supporting substrate.
Flip-chip bonding generally permits a greater density of interconnects per chip than other bonding approaches. The IC chip is bonded to the supporting substrate and the components are held together by the fusing of corresponding solder bumps. The dimension of such a solder bump is typically 80 microns high and 125 microns in diameter. In bonding, two opposing solder bumps are brought into registration and fused together to form a single solder bump spanning between the IC chip and the major substrate. The aspect ratio of the fused solder bump, i.e., the height of the structure divided by its width (diameter), is low, ranging between 1 and 2.
Each of the solder bump connections must be able to withstand the mechanical shearing stresses that are developed by temperature fluctuations and the difference in thermal expansion coefficients between the IC chip and the supporting substrate during operation of the IC chip. Specifically, when the IC chip and the supporting substrate are exposed to elevated temperatures, they will expand at different rates and to different dimensions, thereby inducing mechanical stresses in the solder bump connections. After many thermal cycles or upon large changes in temperature, the fused solder bumps often begin to fatigue and develop cracks. This undesirable development lowers or destroys the electrical conductivity of the fused solder bumps. The cracking usually occurs at the corners of the bases, or ends, of the fused solder bump. The cracking is exacerbated by the low fatigue resistance of solders typically used in IC manufacturing and the low aspect ratio of the fused solder bumps. With regard to the aspect ratio, the shear strain in the solder bump increases as the height of the solder bump decreases, thereby lowering the fatigue resistance capabilities of the joint.
To reduce the thermal stresses, the IC chip and supporting substrate are often constructed from materials having closely matched thermal expansion coefficients so that they expand to substantially the same dimensions when exposed to an elevated temperature. Thermal stresses are still generated each time the IC chip is "powered-up," however, a condition in which a large transient temperature difference between the IC chip and the supporting substrate reaches a temperature near that of the IC chip. Thus, with the high temperatures and power cycling common for high-performance computer chips, solder bumps crack and become mechanically and electrically unreliable even when the IC chip and the supporting substrate have closely matched thermal expansion coefficients. This observation will become a greater problem in the future as computers are designed to dissipate more power in smaller volumes, thereby leading to greater thermal stresses.
Conventional systems require large bonding pad areas, usually 100 microns or more on a side or 100 microns or more in diameter, on the IC chip, on the substrate, or on both components. The large pad areas limit the number of interconnects that can be made to the chip and to the substrate; they also increase the parasitic capacitance of the interconnect. As is known by those skilled in the semiconductor and circuit board industry, the amount of parasitic capacitance of a pad is proportionally related to its area, and the speed at which the interconnect can transmit electrical signals decreases with increasing parasitic capacitance. A modern trend in high-performance computer systems is directed toward increasing the density of chip interconnects and the speed of electrical communications.
Presently, there is a need for a high-density, high-speed wire interconnect structure for electrically and mechanically connecting an integrated circuit to a substrate. There is also a need for a high-density, high-speed wire interconnet structure having improved mechanical and thermal stability. The present invention is directed to filling these needs. Accordingly, one object of the present invention is to provide a wire interconnect structure having a large density of integrated circuit chip interconnects. A related object is to provide a wire interconnect structure having improved mechanical and thermal stability. Still another object of the present invention is to overcome the shortcomings of conventional C-4 interconnect structures.